This invention relates to an output circuit for a semiconductor memory device which can derive data from a memory cell at high speeds.
FIG. 1 shows an output circuit for a conventional semiconductor memory device. A P-channel type MOS transistor 11 and N-channel type MOS transistor 12 are connected in series between a power source terminal V.sub.DD and a power source terminal (ground) V.sub.SS. These MOS transistors are controlled by the output signals of a control circuit 13. The control circuit 13 comprises two inverter circuits 14 and 15 constituting a latch circuit for holding a data signal D which is transferred from a memory cell. Circuit 13 also comprises a NOR gate 16 having one terminal supplied with an output of the inverter 14 and the other terminal supplied with a control signal .phi.1, a NAND gate 18 having one terminal supplied with the output of the inverter 14 and the other terminal supplied with the control signal .phi.1 through an inverter 17, and inverters 19 and 20 for inverting the outputs of the NOR and NAND gates 16 and 18. The MOS transistor 11 is controlled by the output of the inverter 19 and the MOS transistor 12 is controlled by the output of the inverter 20. An output signal Dout is output through a junction between the MOS transistors 11 and 12.
The operation of the above-mentioned circuit arrangement will be explained below:
The circuit arrangement receives a high ("H") level signal as a control signal .phi.1 when data is written into the memory cell. The outputs of the inverters 19 and 20 become "H" and "L" (low) levels, respectively, and in this manner the MOS transistors 11 and 12 are turned OFF. As a result, the output terminal reaches a high impedance state. The circuit arrangement receives the "L" level signal as the control signal .phi.1 when data is read out of the memory cell. When the data signal D, which is input to the latch circuit from the memory cell, reaches a "H" level, the MOS transistor 11 is turned ON and the MOS transistor 12 is turned OFF. An output signal Dout becomes a "H" level signal. When the data signal D is at a "L" level, the MOS transistor 11 is turned OFF and the MOS transistor 12 is turned ON. The output signal Dout becomes a "L" level signal. It should be noted that the output signal Dout is maintained so long as the data signal is being read out by the next address. At the same time the output state remains unchanged. That is, the output signal Dout remains constant until latch data held in the latch circuit varies.
Since, however, the output signal Dout varies between the V.sub.SS level and the V.sub.DD level, a relatively long time is required for the output signal to be set, and high speed operation is difficult to be attained. As the output signal Dout suffers a full swing from the V.sub.DD level to the V.sub.SS level, or vice versa, larger charging or discharging currents flow into the memory device so as to drive a load which is connected to the output terminal of the output circuit. As a result, large internal noises are generated on the internal power source line of the memory device, which causes the operational errors of the memory device.